DEC - 57-19400-08

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DEC

57-19400-08

J-11 microprocessor chip set implementing the PDP-11 instruction set architecture, consisting of a data path and control chip in a hybrid DIP package, used in DEC systems such as the Professional 380.

Specifications

Physical

Package Type
Ceramic hybrid dual inline package (DIP)

Technical

Processor Type
16-bit microprocessor
Architecture
PDP-11 instruction set architecture
Clock Speed
15 MHz
Chip Set Components
Control chip (DC335) and Data path chip (DC334) on a single 60-pin DIP carrier
Floating Point Support
Built-in FP11 floating point support with optional FPJ11 floating point accelerator
Manufacturing Process
CMOS process (fabricated by Intersil)

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